This invention relates to integrated circuits and, more particularly, to configurable storage blocks in an integrated circuit.
Considering a programmable logic device (PLD) as one example of an integrated circuit, as applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized blocks such as configurable storage blocks in addition to blocks of generic programmable logic.
Configurable storage blocks are often arranged in arrays of memory elements. In a typical array, data lines are used to write data into and read data from the configurable storage blocks. Address lines may be used to select which of the memory elements are being accessed. A configurable storage block is typically configurable to implement a memory of a given depth and width, whereby the maximum depth is based on the number of address lanes and the maximum width on the number of data lanes.
Many common memory operations are executed inefficiently using these configurable storage blocks. For example, read-modify-write operations where data is retrieved from memory, modified, and written back to memory may require several clock cycles to complete. The address must usually be provided for the read and the write operation even though the address for the write operation may be known (e.g., if the read and write operations target the same address).
Consequently, it would be desirable to implement a configurable storage block that executes common memory operations more efficiently.